In communication devices, switching elements have been used to switch high frequency signals. Reducing the size of these devices and enhancing their performance therefore requires a high power switching element capable of low voltage operation. A plurality of field effect transistors (hereinafter referred to as “FETs”) may be coupled in series to form such a switching element. However, it is difficult to reduce its size, since the use of a plurality of FETs results in an increased FET area.
To overcome this problem, switching elements having a multigate structure have been proposed. A multigate structure is a structure in which a plurality of gate electrodes is disposed between a pair of ohmic electrodes. Note that it is common to use the double-gate structure, in which two gate electrodes are disposed in parallel relationship. Further, there are several shapes of gate electrodes that can be used in a multigate structure. Crank-shaped gate electrodes are particularly advantageous in terms of reducing the FET area.
The multigate structure is advantageous in that it allows a reduction in the size of the switching elements. However, the potential of the region between the gates varies with position, since it is in a floating state. Therefore, it is not possible to completely turn off conduction between the ohmic electrodes when the FET is put in the off state.
One method for solving this problem has been to couple the n+ region between the gates to the ohmic electrodes by use of potential stabilizing resistances (see for example, JP-A-2006-165224, Laid open patent publication). In this structure, the above n+ region between the gates is held at the same (stabilized) potential as one of the ohmic electrodes.
However, the use of crank-shaped gate electrodes has the following problem. In an FET having a conventional crank-shaped multigate structure, all portions of the crank-shaped gate electrodes function as part of the gates of the FET and hence contribute to its operation. More specifically, for example, when the crank-shaped gate electrodes are disposed on an n-type GaAs layer formed on an insulative semiconductor substrate, both the perpendicularly extending portions and the parallelly extending portions of each gate electrode relative to the [0, 1, 1] crystal orientation of the n-type GaAs layer function as part of the gates of the FET and hence contribute to its operation. Therefore, these perpendicularly and parallelly extending portions must meet the required gate characteristics of the FIT. Specifically, they must have a high dielectric strength voltage (e.g., 10 V or higher).
Incidentally, FETs have employed a recessed structure to achieve enhanced dielectric strength and improved high frequency characteristics. Specifically, in this recessed structure, the n-type active layer is thinner under and around the gate electrodes than under the ohmic electrodes. Such a structure allows a reduction in the source resistance and in the electric field concentration in the drain alloy region.
The recessed structure is formed by wet etching. For example, a silicon oxide film is formed on an n-type semiconductor layer, i.e. an n-type GaAs layer, and then openings are formed through the silicon oxide film to the n-type GaAs layer by photolithography. The exposed n-type GaAs layer is then wet-etched using the silicon oxide film as a mask to form recesses in the n-type GaAs layer. Then, after depositing a gate electrode material, gate electrodes are formed within the recesses by lift-off.
Since the above wet etching is isotropic, the n-type GaAs layer is etched not only in its thickness direction but also in directions perpendicular thereto. However, the etching rate differs in different directions, that is, there is a difference between the amounts of etching in a perpendicular direction and in a parallel direction relative to a crystal orientation of the n-type GaAs layer. It should be noted that which direction provides a larger amount of etching depends on the combination of the crystal orientation of the n-type semiconductor layer and the etchant used.
The difference between the amounts of etching in the perpendicular and parallel directions (relative to the above crystal orientation of the n-type semiconductor layer) results in a difference in width between the portions of the recesses extending in these directions. It should be noted that narrower portions of the recesses have lower dielectric strength voltages. As a result, it is difficult to form the perpendicularly and parallelly extending portions of the recesses (relative to the above crystal orientation of the n-type semiconductor layer) such that both have a sufficient dielectric strength.
Further, in the case of crank-shaped gate electrodes, the electric field concentration at their bent portions reduces the dielectric strength of the gate electrodes even if there is not a significant difference in width between the perpendicularly extending portions and the parallelly extending portions of the recesses in which these gate electrodes are disposed.
The present invention has been devised in view of the above problems. It is, therefore, an object of the present invention to provide an FET having a crank-shaped multigate structure adapted to have improved operating characteristics even if the perpendicularly and parallelly extending portions of the recesses of the n-type semiconductor layer (relative to a crystal orientation of the n-type semiconductor layer) have different widths.
Another object of the present invention is to provide an FET having a crank-shaped multigate structure adapted to have sufficient dielectric strength. Other objects and advantages of the present invention will become apparent from the following description.